Micron plans to use wafer bonding and High-NA EUV for next-gen DRAM

Having jettisoned 4F 2 memory cells from its roadmap, Micron must use different methods to continue scaling its DRAM devices in the coming years to keep up with rivals planning to use smaller DRAM transistors towards the end of the decade. Instead, Micron intends to introduce wafer bonding with its upcoming 1ε DRAM process technology and adopt High-NA EUV lithography for subsequent generations. Meanwhile, the company is developing new types of memory, including vertical high-bandwidth memory (vHBM) and vertical edge inference memory (vEIM), which will be integrated directly on top of processors.

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"DRAM is nearing atomic limits at this point," said Scott DeBoer, president and chief technology and products officer at Micron, during the company's event this week. …